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High-Precision Current-Mode Loser-Take-All & Winner-Take-All Circuits

1.       Introduction

Winner-Take-All (or Looser-Take-All) and MAX (or MIN) circuits are often fundamental building blocks in neural and/or fuzzy hardware systems [2]. Given  a set of N external inputs  (I1 ,I2 , … , IN) , their  performance  consists  of determining which input presents the largest (or smallest) value, or what is this maximum (or minimum) value, respectively.

There are many methods to determine the minimum value, one of which uses subtraction from a fixed current and then selection of maximum current, so it performs as a minimum current selector. The analog subtraction implies loss of accuracy and limits the input current to the value of a fixed reference; moreover it needs large number of MOS transistors, which increases power consumption.

There are two types of structure which have O(N) and O(N2) complexity. The systems with O(N2) occupy more area and consume high power because they grow quadratically  with the number of input currents. Also, due to many devices between input and output stages, the circuit precision decreases. On the other hand, structures with O(N) complexity grow linearly with the number of input currents. This paper presents a new structure for both current-mode LTA and WTA circuits with O(N) complexity which decreases the occupied area and power consumption. It does not need any subtraction of currents; hence precision of the circuit is preserved.

2.       Circuit Description

2.1     Looser-Take-All

The schematic diagram of the proposed LTA circuit is shown in Fig. 1. Only one cell is depicted for simplicity, and this cell will be repeated for every input current. There are N cells which correspond to N inputs (Every cell has 5 MOS transistors as shown), and the   output   stage   is   composed of 2 cascoded devices. This structure uses a simple feedback to identify the minimum value of the input currents. A constant current source is essential for this structure to function.

Fig. 1 Proposed current-mode LTA circuit

Fig. 2 Proposed current-mode WTA circuit

The current source IO  must be larger than each of the input currents. To analyze this circuit, first suppose Iin1 is larger than Iout , so voltage at node “A” rises up to nearly vdd, then M5 goes in cut off region, therefore cell1 makes no changes in Iout. Now suppose that Iin1 is smaller than  Iout, as it seems, voltage at node “A” falls down to nearly GND and then M5 starts to sink the extra current till the output current  Iout  equals to Iin1. This process happens to only one cell which has minimum current. Other cells have no effect on the output. So Iout is always equal to the minimum value of the input currents.

2.2     Winner-Take-All

Fig. 2 shows the proposed current-mode WTA circuit. This structure is similar to the previous (LTA) circuit, but it doesn’t need any current source (IO). To analyse this circuit, first suppose Iin1 is smaller than Iout , so voltage at node “A” falls down to nearly GND, then M5 goes in cut off region and then  cell1 makes no changes in Iout . Now suppose  Iin1 is larger than Iout, as it seems voltage at node “A” rises up to nearly VDD and then M5 starts to feed the current to the current mirror (M6- M7) till the output current Iout equals to Iin1, so Iout is always equal to the maximum value of the input currents.

3.       Simulation Results

Fig. 3 and Fig. 4 are the simulation results of the proposed LTA and WTA circuits with 2 and 3 inputs respectively. These circuits are simulated in 0.35µm standard CMOS process with 3.3V  power supply.

Fig. 3 Simulation Results of LTA circuit

Fig. 4 Simulation Results of WTA circuit

3.2     Stability analysis and compensation

As mentioned before, the proposed structure utilizes a simple feedback to improve precision of the LTA (or WTA) circuit. So stability of the system must be checked to prevent the circuit from any possible oscillating. Loop gain frequency response of the circuit is shown in fig.5.a. Having a transition frequency of 3.21 GHz, gives a phase margin of 34°. as it seems, this phase margin is not enough and it should be increased, so a capacitor is tied between the input and output nodes of the inverter. with a capacitance of 10fF, the transition frequency falls to 1.51 GHz, resulting in a phase margin of 63° (Fig.5.b).

(a)

(b)

Fig. 5 Loop gain frequency response of the circuit

Simulation results show that with this compensation, no further oscillation will occur and the output is stable.

3.3       Monte Carlo analysis of threshold-voltage variations

A statistical distribution of manufacturing parameters always occurs during CMOS fabrication. Because of that, threshold voltages of all MOS transistors were set to nominal values with ±10 variation, and each transistor was given an independent random Gaussian distribution. After 25 Monte Carlo iterations, HSPICE results indicated that circuit precision and speed were not degraded over this range.

4.       Application in Membership Function Generator

In fuzzy applications, Membership Functions (MFs) are used for determination of fuzzy membership value for input variable. Each input should be translated to a specified fuzzy membership value. Typical MFs are defined in trapezoidal or triangular approximations when sketching output versus input variable. In current-current mode, both the input and output values are defined as current. In this case MF can be specified by five different values. By using these values, position and shape of MF are specified. IL and IH are defined as the lowest and the highest value that each of the input currents can take. Imax represents maximum membership value and K1 and K2 are slope values of each side. To form a triangular MF these five values should be defined in such a way that two slops can meet each other before reaching to Imax. "Left slope" is called to the slope beginning at IL and "Right slope" to the slope which ending at IH.

In this MFG, running algorithm is as follows in order to build a typical MF. First of all, Iin is compared with IL and IH. If Iin< IL or Iin>IH the value of output current will be zero. Otherwise two currents according to right and left slopes are produced. Mathematically these two currents are K1.(Iin-IL) and K2.(IH-Iin). Then these currents are compared with Imax. The minimum value among these currents will be the output current. Therefore proposed MFG needs a circuit to generate currents according to right and left slopes and also a Min circuit to compare generated currents with Imax.

4.1         Slope Definition

In order to generate currents according to K1 and K2 the circuits shown in Fig. 6 is used. These circuits are consisting of two current mirrors, which multiply incoming current by value of the slopes. As it mentioned, if Iin does not satisfy IL<Iin<IH, the output current will be zero. In this case, in the circuits shown in Fig. 6, all transistors will be entered in cut-off region and no current will be reflected to ILeft and IRight. Finally the values of generated currents will be:

                 (1)                  (2)

Fig. 6 Schematic of slope definition circuit

4.2         Realization of MFG Using Min Circuits

In the last step of implementation of MFG, the generated currents by slope defining circuits (IRight, ILeft), should be compared with . So a Min circuit is required in order to determine the minimum value among these three currents.

Fig. 7 Block diagram of the MFG circuit

Fig. 8 Simulation results of the proposed MFG

The proposed block diagram of the current mode MFG is showed in Fig. 7.

4.3         Simulation Results

The simulation results of the proposed MFG are shown in Fig. 8. The proposed circuit has the ability to make any triangular and trapezoidal functions with programmable characteristics.

5.       Conclusion

CMOS high-performance current-mode Loser-Take-All and Winner-Take-All circuits are presented. By using a simple feedback, the circuits achieve both high speed and high precision. One application (making a Membership Function Generator) of the LTA circuit had been shown in the paper. A 3.3V­ power supply has been applied and simulation results are presented in .35µm CMOS process.

References

[1] B. Kosko, Neural Networks and Fuzzy Systems. Englewood Cliffs, NJ: Prentice-Hall, 1992.

[2] T. Gotarredona and B. Barranco”A High-Precision Current-Mode WTA-MAX Circuit with Multichip Capability” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998.

[3] C. Chen, Y. Hsieh, and B. Liu, “Circuit Implementation of Linguistic-Hedge Fuzzy Logic Controller in Current-Mode Approach” IEEE TRANS. FUZZY SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003.

[4] J. Lazzaro., S. Ryckebusch, M. A. Mahowald, and C.A. Mead, “Winner-tale-all networks of O(n) complexity”, ed. D.S.Touretzky, Morgan Kaumann, San Mateo, CA, 1:703- 711, 1989.

[5] M. Kachare, J. Ramírez-Angulo, R.Gonzalez Carvajal and A. J. López-Martín, “New Low-Voltage Fully Programmable CMOS Triangular/Trapezoidal Function Generator Circuit” IEEE Trans. CIRCUITS AND SYSTEMS. VOL. 52, NO. 10, OCTOBER 2005.

About the Author

Name: Amir Kousari
Email: amir_kousari@yahoo.com
Urmia university of Iran, Urmia.

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